1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit and, more particularly, to an ESD protection circuit that includes fully distributed slave ESD clamps that are formed under the bond pads.
2. Description of the Related Art
An electrostatic discharge (ESD) protection circuit is a circuit that protects the input/output (I/O) transistors of a semiconductor chip from an ESD event. An ESD event typically occurs when the chip is exposed to static electricity, such as when the pins or solder bumps of the chip are touched by an ungrounded person handling the chip, or when the chip slides across another surface on its pins or solder bumps.
For example, an ungrounded person handling a semiconductor chip can place a static electric charge as high as 2000V on the chip. This voltage is more than sufficient to destructively break down the gate oxide of the input/output transistors of the chip.
FIG. 1 shows a schematic diagram that illustrates a prior-art ESD protection circuit 100. As shown in FIG. 1, circuit 100, which provides ESD protection to a power pad 102, a ground pad 104, and a number of I/O pads 106, includes an ESD plus ring 110 and an ESD minus ring 112 that extend around the periphery of a semiconductor chip 114.
As further shown in FIG. 1, ESD protection circuit 100 includes a plurality of upper diodes D1 that are connected to ESD plus ring 110 and the pads 102, 104, and 106 so that each pad is connected to ESD plus ring 110 via a diode D1. In addition, a plurality of lower diodes D2 are connected to ESD minus ring 112 and the pads 102, 104, and 106 so that each pad is connected to ESD minus ring 112 via a diode D2. Circuit 100 also includes four corner clamps 116 that are connected to ESD plus ring 110 and ESD minus ring 112.
In operation, when an ESD event occurs, a first pad A, for example, is zapped positively with respect to a second pad B. In this situation, a zap current IZAP flows from first pad A through the adjacent diode D1 to ESD plus ring 110, and then on to the corner clamps 116. The corner clamps 116 are voltage controlled switches that each provide a low impedance pathway from ESD positive ring 110 to ESD negative ring 112 when an ESD event is present, and a high impedance pathway between rings 110 and 112 when an ESD event is not present.
When first pad A is zapped, the corner clamps 116 (which are shown open, not closed, in FIG. 1) close and the zap current IZAP flows through clamps 116 to ESD minus ring 112. From ring 112, the zap current IZAP flows through the diode D2 adjacent to second pad B, and then onto second pad B.
FIG. 2 shows a schematic diagram that illustrates an example of corner clamp 116. As shown in FIG. 2, clamp 116 includes a RC timing circuit 210, an inverter 212, and a switching transistor M1. Timing circuit 210, in turn, includes a resistor R that is connected to an ESD plus ring, such as ESD plus ring 110, and a capacitor C that is connected to resistor R and an ESD minus ring, such as ESD minus ring 112.
Inverter 212 includes a PMOS transistor M2 and a NMOS transistor M3. Transistor M2 has a source connected to ESD plus ring 110, a gate connected to resistor R and capacitor C, and a drain. Transistor M3 has a source connected to ESD minus ring 112, a gate connected to resistor R and capacitor C, and a drain connected to the drain of transistor M2. Further, switching transistor Ml has a source connected to ESD minus ring 112, a gate connected to the drains of transistors M2 and M3, and a drain connected to ESD plus ring 110.
In operation, when an ESD event occurs and the zap current IZAP flows onto ESD plus ring 110, the voltage on ESD plus ring 110 spikes up dramatically. The voltage on the gates of transistors M2 and M3 also spikes up but, due to the presence of RC timing circuit 110, the gate voltage lags the voltage on ESD plus ring 110.
As a result, the gate-to-source voltage of transistor M2 falls below the threshold voltage of transistor M2, thereby turning on transistor M2 for as long as the gate voltage lags the voltage on ring 110. When transistor M2 turns on, transistor M2 pulls up the voltage on the gate of transistor M1, thereby turning on transistor M1. When transistor M1 is turned on, clamp 200 provides a low impedance pathway from ESD plus ring 110 to ESD minus ring 112.
The ESD protection circuitry used on a semiconductor chip is commonly considered to be part of the I/O cell structure of the chip. Typically, each I/O cell includes a pad, such as power pad 102, ground pad 104, or an I/O pad 106, a section of an ESD plus ring, such as ring 110, and a section of an ESD minus ring, such as ring 112.
In addition, each I/O cell includes an upper diode, such as diode D1, that is connected between the pad and the ESD plus ring, and a lower diode, such as diode D2, that is connected between the pad and the ESD minus ring. Further, each I/O cell includes a section of a clean power ring, and a section of a clean ground ring. The clean power ring, which is supplied by a first power pad, and the clean ground ring, which is connected to a first ground pad, support the core circuitry of the semiconductor chip with substantially noise free power and ground connections.
Each I/O cell also includes a section of a dirty power ring, and a section of a dirty ground ring. The dirty power ring, which is supplied by a second power pad, and the dirty ground ring, which is connected to a second ground pad, support the noisy I/O circuits. In addition, each I/O cell typically includes I/O circuitry.
FIGS. 3A-3F show a series of plan views that illustrate an example of the physical layout of a prior art I/O cell 300. As shown in FIG. 3A, I/O cell 300, which is formed in a layer of semiconductor material 302, includes a diode 304, such as diode D1 of FIG. 1, that is formed in material 302. In addition, I/O cell 300 includes a diode 306, such as diode D2 of FIG. 1, that is formed in material 302.
Further, I/O cell 300 includes I/O circuitry 312 that is formed in semiconductor material 302. I/O circuitry 312 can include, for example, MOS and/or bipolar transistors. Cell 300 also includes a number of contacts 314 that are formed through a first layer of dielectric material to make an electrical connection with diodes 304 and 306 and I/O circuitry 312.
Referring to FIG. 3B, I/O cell 300 additionally includes a first pad P1 and a number of first regions 316 that are formed from a first layer of metal. Pad P1 and the first regions 316, which include first regions 316A and 316B, are formed so that pad P1 and the first regions 316 make electrical connections with contacts 314. Cell 300 also includes a number of vias 320 that are formed through a second layer of dielectric material to make electrical connections with pad P1 and the first regions 316.
Referring to FIG. 3C, I/O cell 300 additionally includes a second pad P2 and a number of second regions 322 that are formed from a second layer of metal. Pad P2 and the second regions 322, which include second regions 322-A, 322-B, and 322-C, are formed so that pad P2 and the second regions 322 make electrical connections with vias 320.
Cell 300 also includes a trace 324 that is formed from the second layer of metal. Trace 324 is connected to pad P2, second region 322-A, and second region 322-B. Cell 300 also includes a number of vias 330 that are formed through a third layer of dielectric material to make electrical connections with pad P2 and the second regions 322.
Referring to FIG. 3D, I/O cell 300 further includes a third pad P3, a section of a first ESD plus ring 340, and a section of a first ESD minus ring 342. In addition, I/O cell 300 includes a section of clean power line 344, and a section of a clean ground line 346. Further, I/O cell 300 includes a section of a dirty power line 350, and a section of a dirty ground line 352. Pad P3, rings 340 and 342, and lines 344, 346, 350, and 352 are formed from a third layer of metal.
Pad P3, rings 340 and 342, and lines 344, 346, 350, and 352 are also formed to make electrical connections with vias 330. Cell 300 additionally includes a number of vias 354 that are formed through a fourth layer of dielectric material to make electrical connections with pad P3, rings 340 and 342, and lines 344, 346, 350, and 352.
Referring to FIG. 3E, I/O cell 300 additionally includes a fourth pad P4, a second ESD plus ring 360, and a second ESD minus ring 362. In addition, I/O cell 300 includes a clean power line 364, a clean ground line 366, a dirty power line 370, and a dirty ground line 372. Pad P4, rings 360 and 362, and lines 364, 366, 370, and 372 are formed from a fourth layer of metal.
Pad P4, rings 360 and 362, and lines 364, 366, 370, and 372 are also formed to make electrical connections with vias 354. Cell 300 also includes a number of vias 374 that are formed through a fifth layer of dielectric material to make electrical connections with pad P4, rings 360 and 362, and lines 364, 366, 370, and 372.
Referring to FIG. 3F, I/O cell 300 further includes a fifth pad P5, a third ESD plus ring 380, and a third ESD minus ring 382. In addition, I/O cell 300 includes a clean power line 384, a clean ground line 386, a dirty power line 390, and a dirty ground line 392. Pad P5, rings 380 and 382, and lines 384, 386, 390, and 392 are formed from a fifth layer of metal. Pad P5, rings 380 and 382, and lines 384, 386, 390, and 392 are also formed to make electrical connections with vias 374.
Together, pads P1-P5 form a bonding pad, such as pad 102 of FIG. 1. Together, ESD plus rings 340, 360, and 380 form an ESD plus ring, such as ring 110. Together, ESD minus rings 342, 362, and 382 form an ESD minus ring, such as ring 112.
As further shown in FIG. 3F, I/O cell 300 has an I/O cell height X that is measured laterally from the edge of the die and includes the widths of pad P5, rings 380 and 382, and lines 384, 386, 390, and 392. Pad P5, the pair of rings 380 and 382, the pair of lines 384 and 386, and the pair of lines 390 and 392 each require about the same amount of silicon real estate.
In operation, when an ESD event occurs on pad P5, the voltage spike passes through vias 374 to pad P4, and from pad P4 through vias 354 to pad P3. The voltage spike continues through vias 330 to pad P2, and from pad P2 through trace 324 to region 322A. The spike continues through vias 320 to region 316A, and from region 316A through contact 314 to diode D1.
The voltage spike passes through diode D1, through contact 314 to region 316-B, and from region 316-B to via 320, and then to region 322-B. From region 322-B, the spike continues to via 330, and then to ESD plus ring 340. From ESD plus ring 340, the spike moves to ESD plus rings 360 and 380 by vias 354 and 374.
Although ESD protection circuit 100, corner clamp 116, and I/O cell 300 function satisfactorily, there is a need for alternate ESD protection circuits and layouts.
The present invention provides an ESD protection circuit that protects the pads of a semiconductor die from an electrostatic discharge (ESD) event. An electrostatic discharge (ESD) protection circuit in accordance with the present invention includes an ESD plus ring and an ESD minus ring that are formed on the die around the periphery of the die. The ESD protection circuit also includes a trigger ring that is formed on the die around the periphery of the die, and a plurality of first clamps that are formed on the die.
Each first clamp has a first diode and a spaced-apart second diode that are formed on the die. The first diode is connected to a pad and the ESD plus ring, while the second diode is connected to the pad and the ESD minus ring. Each first clamp also has a first transistor and a second transistor. The first transistor is connected to the ESD plus ring, the trigger ring, and a first node. The second transistor is connected to the ESD minus ring, the trigger ring, and the first node. Each first clamp further includes a third transistor that is connected to the ESD plus ring, the ESD minus ring, and the first node.